The mainframe architecture that keeps global commerce running for decades

Science · Published 1 November 2026 Swipe more like this →

In short: While modern computing often favors the new, IBM's z/Architecture is a masterclass in architectural endurance. It manages to power today's most demanding enterprise workloads while remaining backward compatible with systems from the 1960s. It isn't just old technology; it is a sophisticated evolution of high-performance engineering.

Introduced in late 2000 with the z900, z/Architecture is IBM's 64-bit complex instruction set computer (CISC) architecture. Unlike many modern architectures that prioritize simplicity to gain speed, z/Architecture was designed for massive scale and reliability. It serves as the backbone for mainframe computers, including recent models like the z17. A defining characteristic of this architecture is its extreme backward compatibility; it supports legacy 32-bit-data and 31-bit-addressing from the ESA/390 era, and even reaches back to the System/360 architecture.

The technical evolution of the z/Architecture is a study in expansion. It incorporates nearly all features of its predecessors while adding specialized hardware for modern needs. For example, it expanded 32-bit control registers into 64-bit versions and introduced 128-bit vector registers (VRs). A notable milestone occurred with the z13, which introduced a 128-bit Packed SIMD facility called the "Vector Facility." This added over 150 new instructions for integer, floating-point, and string data types, utilizing two independent SIMD units to handle complex calculations.

The architecture continues to adapt to emerging technologies like artificial intelligence. The z16 introduced a Neural-network-processing-assist facility, providing specific instructions for tensor operations used in AI applications. Despite these leaps forward—from 64-bit general registers to specialized neural network processing—the system ensures that application programs originally written for the ESA/390 architecture remain unaffected by these changes. This balance of cutting-edge capability and historical continuity is what allows it to sustain global infrastructure.

Mechanically, the architecture relies on complex register management and memory addressing. It utilizes 16 32-bit access registers (ARs) for address translation and a unique Breaking-event-address register (BEAR). The BEAR specifically stores the address of the last instruction that interrupted sequential execution, providing a precise hook for the system to manage interrupts and branches efficiently.

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